There are many situations where it is desirable to interconnect corresponding leads of integrated circuit (IC) packages in a manner which optimizes use of printed circuit board (PCB) space. These situations include increasing the memory capabilities of a computer system, increasing performance by combining, for example, a microprocessor and a math co-processor, or upgrading a system by disabling the older microprocessor on the PCB and running a newer and faster microprocessor.
Integrated circuit packages come in leadless or leaded configurations. A leadless IC package contains no leads but rather, contains conductive pads on the edges of the package for interconnection to a PCB. Leaded packages, on the other hand, have leads which project outwardly from the body of the package.
Leaded IC packages can be formed in various configurations. A typical configuration is the dual in-line package (DIP). The DIP comprises an IC interconnected to a lead frame, enclosed within a dielectric body with leads partially enclosed within the body. The IC package body generally includes a top and a bottom surface, sidewalls and endwalls. The DIP leads typically extend outwardly from the sidewalls and bend downwardly. The leads are placed in opposed parallel rows and typically range from 4-80 leads per package.
Increases in IC complexity have placed more functionality on a chip than a DIP and its relatively low number of leads can accommodate. Pin grid arrays (PGA) with over 200 leads extending directly from the bottom surface of an IC package are in common use. Square or rectangular packages such as the Plastic Quad Flat Pack (PQFP) and other package types having a plastic body formed in a rectangle are used in many applications.
Alternative IC packages, such as the PQFP, have leads extending outwardly at all four sidewalls as opposed to just two sidewalls as in the DIP design. The lead ends (as on the PQFP) are often bent to form feet parallel to the top and bottom surfaces and parallel to the PCB on which they are mounted. The pitch, or distance between adjacent leads, on the packages is typically on the order of 0.020-0.025 inches.
The alternative packages and increased lead densities reflect the premium placed on printed circuit board space and the desire to minimize area consumed by electronics. As well, non-packaging mechanical schemes have been devised for minimizing area consumed by electronics while permitting the supplementing, upgrading and/or overriding of existing circuitry mounted on a PCB.
It is known to stack DIP components, as suggested by U.S. Pat. No. 4,406,508 and U.S. Pat. No. 4,696,525. However, such known methodologies do not address problems inherent in stacking components configured in alternative packages. With the small pitch distance between pins on many packages and the presence of pins on all four sides of the packages, significant alignment problems arise. Generally, in order to connect one PQFP device to another it is necessary that there be a one to one connection of pins, for example, pin 1 to pin 1, pin 160 to pin 160, etc. Known devices for stacking DIPs use the lower portions of endwalls to orient the connector. However, with a square or rectangular package with electrical contacts on all sides, there are no endwalls for alignment purposes.
Additional problems arise in known DIP stacking devices because of susceptibility to mechanical loosening. Devices in the top position can become loose either due to thermal expansion or vibration which can lead to reliability and performance problems.
Various other problems arise, relating to electrical continuity and shorting of leads in high pin count DIPs, so that a skilled technician is sometimes needed to install the packages in order to connect or stack two IC packages. Pressure often must be exerted on the packages for seating to be exact, however, pushing too hard or applying too much pressure can either bend the leads so as to cause non-connections and short circuits, and/or decreased reliability.